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| MCP4902/4912/4922 8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter with SPI Interface Features * * * * * * * * * * * * MCP4902: Dual 8-Bit Voltage Output DAC MCP4912: Dual 10-Bit Voltage Output DAC MCP4922: Dual 12-Bit Voltage Output DAC Rail-to-Rail Output SPI Interface with 20 MHz Clock Support Simultaneous Latching of the Dual DACs with LDAC pin Fast Settling Time of 4.5 s Selectable Unity or 2x Gain Output External Voltage Reference Inputs External Multiplier Mode 2.7V to 5.5V Single-Supply Operation Extended Temperature Range: -40C to +125C Description The MCP4902/4912/4922 devices are dual 8-bit, 10-bit, and 12-bit buffered voltage output Digital-to-Analog Converters (DACs), respectively. The devices operate from a single 2.7V to 5.5V supply with SPI compatible Serial Peripheral Interface. The user can configure the full-scale range of the device to be VREF or 2 * VREF by setting the Gain Selection Option bit (gain of 1 of 2). The user can shut down both DAC channels by using SHDN pin or shut down the DAC channel individually by setting the Configuration register bits. In Shutdown mode, most of the internal circuits in the shutdown channel are turned off for power savings and the output amplifier is configured to present a known high resistance output load (500 ktypical. The devices include double-buffered registers, allowing synchronous updates of two DAC outputs, using the LDAC pin. These devices also incorporate a Power-on Reset (POR) circuit to ensure reliable powerup. The devices utilize a resistive string architecture, with its inherent advantages of low DNL error and fast settling time. These devices are specified over the extended temperature range (+125C). The devices provide high accuracy and low noise performance for consumer and industrial applications where calibration or compensation of signals (such as temperature, pressure and humidity) are required. The MCP4902/4912/4922 devices are available in the PDIP, SOIC and TSSOP packages. Applications * * * * * Set Point or Offset Trimming Precision Selectable Voltage Reference Motor Control Feedback Loop Digitally-Controlled Multiplier/Divider Calibration of Optical Communication Devices Related Products(1) P/N MCP4801 MCP4811 MCP4821 MCP4802 MCP4812 MCP4822 MCP4901 MCP4911 MCP4921 MCP4902 MCP4912 MCP4922 DAC No. of Resolution ChannelS 8 10 12 8 10 12 8 10 12 8 10 12 1 1 1 2 2 2 1 1 1 2 2 2 External Internal (2.048V) Voltage Reference (VREF) Package Types 14-Pin PDIP, SOIC, TSSOP VDD 1 NC 2 CS 3 SCK 4 SDI 5 NC 6 NC 7 14 VOUTA MCP49X2 13 VREFA 12 VSS 11 VREFB 10 VOUTB 9 SHDN 8 LDAC Note 1: The products listed here have similar AC/ DC performances. MCP4902: 8-bit dual DAC MCP4912: 10-bit dual DAC MCP4922: 12-bit dual DAC 2010 Microchip Technology Inc. DS22250A-page 1 MCP4902/4912/4922 Block Diagram LDAC CS SDI SCK Interface Logic Power-on Reset VDD Input Register A Input Register B DACB Register VSS DACA Register VREF A Buffer Gain Logic String DACA String DACB VREF B Buffer Gain Logic Output Op Amps Output Logic VOUTA SHDN VOUTB DS22250A-page 2 2010 Microchip Technology Inc. MCP4902/4912/4922 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD....................................................................... 6.5V All inputs and outputs w.r.t ..... VSS -0.3V to VDD+0.3V Current at Input Pins ......................................... 2 mA Current at Supply Pins .................................... 50 mA Current at Output Pins .................................... 25 mA Storage temperature .......................... -65C to +150C Ambient temp. with power applied ..... -55C to +125C ESD protection on all pins 4 kV (HBM), 400V (MM) Maximum Junction Temperature (TJ)................+150C ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85C. Typical values are at +25C. Parameters Power Requirements Operating Voltage Operating CurrentInput Current Sym VDD IDD Min 2.7 -- -- Typ -- 350 250 Max 5.5 700 500 Units V A A Conditions VDD = 5V VDD = 3V VREF input is unbuffered, all digital inputs are grounded, all analog outputs (VOUT) are unloaded. Code = 000h. Power-on Reset circuit is turned off Power-on Reset circuit stays on Hardware Shutdown Current Software Shutdown Current Power-on-Reset Threshold DC Accuracy MCP4902 Resolution INL Error DNL MCP4912 Resolution INL Error DNL MCP4922 Resolution INL Error DNL Offset Error Note 1: 2: ISHDN ISHDN_SW VPOR -- -- -- 0.3 3.3 2.0 2 6 -- A A V n INL DNL n INL DNL n INL DNL VOS 8 -1 -0.5 10 -3.5 -0.5 12 -12 -0.75 -- -- 0.125 0.1 -- 0.5 0.1 -- 2 0.2 0.02 -- 1 +0.5 -- 3.5 +0.5 -- 12 +0.75 1 Bits LSb LSb Bits LSb LSb Bits LSb LSb % of FSR Note 1 Code = 0x000h Note 1 Note 1 Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested. 2010 Microchip Technology Inc. DS22250A-page 3 MCP4902/4912/4922 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85C. Typical values are at +25C. Parameters Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range - Buffered Mode Input Range - Unbuffered Mode Input Impedance Input Capacitance - Unbuffered Mode Multiplier Mode -3 dB Bandwidth Sym VOS/C gE G/C Min -- -- -- -- Typ 0.16 -0.44 -0.10 -3 Max -- -- 1 -- Units ppm/C ppm/C % of FSR ppm/C Conditions -45C to 25C +25C to 85C Code = 0xFFFh, not including offset error VREF VREF RVREF CVREF fVREF fVREF 0.040 0 -- -- -- -- -- -- -- 165 7 450 400 -73 VDD - 0.040 VDD -- -- -- -- -- V V k pF kHz kHz dB Note 2 Code = 2048 VREF = 0.2V p-p, f = 100 Hz and 1 kHz Unbuffered Mode VREF = 2.5V 0.2Vp-p, Unbuffered, G = 1x VREF = 2.5V 0.2 Vp-p, Unbuffered, G = 2x VREF = 2.5V 0.2Vp-p, Frequency = 1 kHz Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD - 40 mV) Multiplier Mode - Total Harmonic Distortion Output Amplifier Output Swing Phase Margin Slew Rate Short Circuit Current Settling Time THDVREF VOUT m SR ISC tsettling -- -- -- -- -- 0.01 to VDD - 0.04 66 0.55 15 4.5 -- -- -- 24 -- V degrees V/s mA s Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Dynamic Performance (Note 2) DAC-to-DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note 1: 2: -- -- -- -- 10 45 10 10 -- -- -- -- nV-s nV-s nV-s nV-s 1 LSb change around major carry (0111...1111 to 1000...0000) Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested. DS22250A-page 4 2010 Microchip Technology Inc. MCP4902/4912/4922 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125C by characterization or simulation. Parameters Power Requirements Operating Voltage Operating Current Sym VDD IDD Min 2.7 -- Typ -- 400 Max 5.5 -- Units V A Conditions VREF input is unbuffered, all digital inputs are grounded, all analog outputs (VOUT) are unloaded. Code=000h POR circuit is turned-off POR circuit stays turned-on Hardware Shutdown Current ISHDN -- -- -- 1.5 5 1.85 -- -- -- A A V Software Shutdown Current ISHDN_SW Power-On Reset threshold VPOR DC Accuracy MCP4902 Resolution INL Error DNL MCP4912 Resolution INL Error DNL MCP4922 Resolution INL Error DNL Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range - Buffered Mode VREF n INL DNL VOS VOS/C gE G/C n INL DNL n INL DNL 8 -- 0.25 0.2 -- Bits LSb LSb Note 1 10 -- 1 0.2 -- Bits LSb LSb Note 1 12 -- 4 0.25 -- Bits LSb LSb Note 1 Code 0x000h +25C to +125C Code = 0xFFFh, not including offset error -- -- -- -- 0.02 -5 -0.10 -3 -- -- -- -- % of FSR ppm/C % of FSR ppm/C -- 0.040 to VDD - 0.040 -- V Note 1 Code = 2048, VREF = 0.2V p-p, f = 100 Hz and 1 kHz Input Range - Unbuffered Mode Input Impedance Input Capacitance - Unbuffered Mode Note 1: 2: VREF RVREF CVREF 0 -- -- -- 174 7 VDD -- -- V k pF Unbuffered mode Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested. 2010 Microchip Technology Inc. DS22250A-page 5 MCP4902/4912/4922 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125C by characterization or simulation. Parameters Multiplying Mode -3 dB Bandwidth Sym fVREF fVREF Min -- -- -- Typ 450 400 -- Max -- -- -- Units kHz kHz dB Conditions VREF = 2.5V 0.1 Vp-p, Unbuffered, G = 1x VREF = 2.5V 0.1 Vp-p, Unbuffered, G = 2x VREF = 2.5V 0.1Vp-p, Frequency = 1 kHz Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD - 40 mV) Multiplying Mode - Total Harmonic Distortion Output Amplifier Output Swing Phase Margin Slew Rate Short Circuit Current Settling Time THDVREF VOUT m SR ISC tsettling -- -- -- -- -- 0.01 to VDD - 0.04 66 0.55 17 4.5 -- -- -- -- -- V degrees V/s mA s Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Dynamic Performance (Note 2) DAC to DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note 1: 2: -- -- 10 45 -- -- nV-s nV-s 1 LSb change around major carry (0111...1111 to 1000...0000) -- -- 10 10 -- -- nV-s nV-s Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested. DS22250A-page 6 2010 Microchip Technology Inc. MCP4902/4912/4922 AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, VDD= 2.7V - 5.5V, TA= -40 to +125C. Typical values are at +25C. Parameters Schmitt Trigger High-Level Input Voltage (All digital input pins) Schmitt Trigger Low-Level Input Voltage (All digital input pins) Hysteresis of Schmitt Trigger Inputs Input Leakage Current Digital Pin Capacitance (All inputs/outputs) Clock Frequency Clock High Time Clock Low Time CS Fall to First Rising CLK Edge Data Input Setup Time Data Input Hold Time SCK Rise to CS Rise Hold Time CS High Time LDAC Pulse Width LDAC Setup Time SCK Idle Time before CS Fall Note 1: Sym VIH Min 0.7 VDD Typ -- Max -- Units V Conditions VIL -- -- 0.2 VDD V VHYS ILEAKAGE CIN, COUT FCLK tHI tLO tCSSR tSU tHD tCHS tCSH tLD tLS tIDLE -- -1 -- -- 15 15 40 15 10 15 15 100 40 40 0.05 VDD -- 10 -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 20 -- -- -- -- -- -- -- -- -- -- V A pF MHz ns ns ns ns ns ns ns ns ns ns SHDN = LDAC = CS = SDI = SCK + VREF = VDD or VSS VDD = 5.0V, TA = +25C, fCLK = 1 MHz (Note 1) TA = +25C (Note 1) Note 1 Note 1 Applies only when CS falls with CLK high. (Note 1) Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 This parameter is ensured by design and not 100% tested. tCSH CS tCSSR Mode 1,1 SCK Mode 0,0 tSU SI MSb in LSb in tHD tIDLE tHI tLO tCHS LDAC tLS tLD FIGURE 1-1: SPI Input Timing Data. 2010 Microchip Technology Inc. DS22250A-page 7 MCP4902/4912/4922 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1: JA JA JA -- -- -- 70 120 100 -- -- -- C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Note 1 Sym Min Typ Max Units Conditions The MCP4902/4912/4922 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the maximum junction temperature of 150C. DS22250A-page 8 2010 Microchip Technology Inc. MCP4902/4912/4922 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 0.3 Absolute DNL (LSB) 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 0 1024 2048 Code (Decimal) 3072 4096 0.0766 0.0764 0.0762 0.076 0.0758 0.0756 0.0754 0.0752 0.075 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) FIGURE 2-1: DNL vs. Code (MCP4922). FIGURE 2-4: Absolute DNL vs. Temperature (MCP4922). 0.35 Absolute DNL (LSB) 0.3 0.25 0.2 0.15 0.1 0.05 0 1 2 3 4 5 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 0 1024 2048 3072 125C 85C 4096 25C Code (Decimal) Voltage Reference (V) FIGURE 2-2: DNL vs. Code and Temperature (MCP4922). 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 1 FIGURE 2-5: Absolute DNL vs. Voltage Reference (MCP4922). 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 1024 Ambient Temperature 125C 85 25 3072 2 3 4 4096 5.5 INL (LSB) Code (Decimal) 2048 3072 Code (Decimal) 4096 FIGURE 2-3: DNL vs. Code and VREF, Gain = 1 (MCP4922). FIGURE 2-6: INL vs. Code and Temperature (MCP4922). 2010 Microchip Technology Inc. DS22250A-page 9 MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 2.5 Absolute INL (LSB) 2 1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 120 INL (LSB) 2 0 -2 -4 -6 0 1024 2048 Code (Decimal) 3072 4096 Ambient Temperature (C) FIGURE 2-7: Absolute INL vs. Temperature (MCP4922). FIGURE 2-10: Note: INL vs. Code (MCP4922). Single device graph (Figure 2-10) for illustration of 64 code effect. 3 0.2 Absolute INL (LSB) 2.5 2 1.5 1 0.5 0 DNL (LSB) 0.1 Temp = - 40oC to +125oC 0 -0.1 1 2 3 4 5 -0.2 0 128 256 384 512 640 Code 768 896 1024 Voltage Reference (V) FIGURE 2-8: (MCP4922). 3 2 1 INL (LSB) Absolute INL vs. VREF FIGURE 2-11: DNL vs. Code and Temperature (MCP4912). VREF 1 2 3 4 5.5 1.5 0.5 INL (LSB) -0.5 -1.5 -2.5 - 40 C o 85 C o 0 -1 -2 -3 -4 0 1024 2048 3072 Code (Decimal) 4096 25 C o 125 C o -3.5 0 128 256 384 512 640 Code 768 896 1024 FIGURE 2-9: (MCP4922). INL vs. Code and VREF FIGURE 2-12: INL vs. Code and Temperature (MCP4912). DS22250A-page 10 2010 Microchip Technology Inc. MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 0 32 64 96 128 160 192 224 256 Code Temp = -40oC to +125oC 20 18 16 14 12 10 8 6 4 2 0 215 225 235 245 255 265 275 285 295 305 315 400 415 IDD (A) 325 FIGURE 2-13: DNL vs. Code and Temperature (MCP4902). 0.5 -40 C to +85 C o o DNL (LSB) Occurrence FIGURE 2-16: IDD Histogram (VDD = 2.7V). 16 14 12 Occurrence 125 C o 0.25 INL (LSB) 10 8 6 4 2 0 250 265 280 295 310 325 340 355 370 385 0 -0.25 -0.5 0 32 64 96 128 160 Code 192 224 256 IDD (A) FIGURE 2-14: INL vs. Code and Temperature (MCP4902). 400 350 IDD (A) 300 250 200 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) FIGURE 2-17: 5.0V). IDD Histogram (VDD = 5.5V 5.0V 4.0V 3.0V 2.7V VDD FIGURE 2-15: VDD. IDD vs. Temperature and 2010 Microchip Technology Inc. DS22250A-page 11 MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 2 5.5V -0.08 5.0V VDD 5.5V Gain Error (%) 1.5 ISHDN (A) -0.1 5.0V 1 4.0V 3.0V 2.7V -0.12 4.0V 3.0V 2.7V 0.5 VDD -0.14 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) -0.16 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) FIGURE 2-18: Hardware Shutdown Current vs. Ambient Temperature and VDD. 6 5.5V FIGURE 2-21: Gain Error vs. Ambient Temperature and VDD. 4 VDD 5.5V 5.0V 5 ISHDN_SW (A) 4 3 2 5.0V VIN Hi Threshold (V) 3.5 3 2.5 2 1.5 1 4.0V 3.0V 2.7V VDD 4.0V 1 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) 3.0V 2.7V -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) FIGURE 2-19: Software Shutdown Current vs. Ambient Temperature and VDD. 0.12 FIGURE 2-22: VIN High Threshold vs Ambient Temperature and VDD. 1.6 VIN Low Threshold (V) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) 3.0V 2.7V 4.0V 0.1 Offset Error (%) 0.08 0.06 0.04 0.02 0 -0.02 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) 5.0V 4.0V 3.0V 2.7V VDD VDD 5.5V 5.0V 5.5V FIGURE 2-20: Offset Error vs. Ambient Temperature and VDD. FIGURE 2-23: VIN Low Threshold vs Ambient Temperature and VDD. DS22250A-page 12 2010 Microchip Technology Inc. MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) 0.0045 VOUT_LOW Limit (Y-AVSS)(V) 0.004 0.0035 0.003 5.0V VDD 5.5V 5.0V 4.0V 3.0V 2.7V VDD 5.5V VIN_SPI Hysteresis (V) 0.0025 0.002 0.0015 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) 4.0V 3.0V 2.7V FIGURE 2-24: Input Hysteresis vs. Ambient Temperature and VDD. 175 VREF_UNBUFFERED Impedance (kOhm) FIGURE 2-27: VOUT Low Limit vs. Ambient Temperature and VDD. 18 IOUT_HI_SHORTED (mA) VDD 5.5V 5.0V 4.0V 3.0V 2.7V 5.5V 2.7V VDD 17 16 15 14 13 12 11 10 170 165 160 155 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) FIGURE 2-25: VREF Input Impedance vs. Ambient Temperature and VDD. 0.045 VOUT_HI Limit (VDD-Y)(V) 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) FIGURE 2-28: IOUT High Short vs. Ambient Temperature and VDD. 6.0 5.0 VREF=4.0 5.5V 5.0V 4.0V VOUT (V) 4.0 Output Shorted to VDD 3.0V 2.7V VDD 3.0 2.0 1.0 0.0 0 2 4 6 8 10 IOUT (mA) 12 14 16 Output Shorted to VSS FIGURE 2-26: VOUT High Limit vs. Ambient Temperature and VDD. FIGURE 2-29: IOUT vs VOUT. Gain = 1x. 2010 Microchip Technology Inc. DS22250A-page 13 MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. VOUT VOUT SCK LDAC Time (1 s/div) LDAC Time (1 s/div) FIGURE 2-30: VOUT Rise Time. FIGURE 2-33: VOUT Rise Time. VOUT VOUT SCK SCK LDAC Time (1 s/div) LDAC Time (1 s/div) FIGURE 2-31: VOUT Fall Time. FIGURE 2-34: Shutdown. VOUT Rise Time Exit VOUT SCK LDAC Time (1 s/div) Ripple Rejection (dB) Frequency (Hz) FIGURE 2-32: VOUT Rise Time. FIGURE 2-35: PSRR vs. Frequency. DS22250A-page 14 2010 Microchip Technology Inc. MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = 2.50V, Gain = 2x, RL = 5 k, CL = 100 pF. 0 0 -2 Attenuation (dB) -4 -6 -8 -10 -12 100 D= D= D= D= D= D= D= D= D= D= D= D= D= D= D= 160 416 672 928 1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744 -45 qVREF - qVOUT -90 -135 Frequency (kHz) 1,000 -180 100 D= D= D= D= D= D= D= D= D= D= D= D= D= D= D= 160 416 672 928 1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744 Frequency (kHz) 1,000 FIGURE 2-36: Note: Multiplier Mode Bandwidth. FIGURE 2-38: Phase Shift. Dn * G VOUT Attenuation (dB) = 20 log ( - 20 log ( 4096 ) VREF ) 600 580 560 540 520 500 480 460 440 420 400 Bandwidth (kHz) G=1 G=2 FIGURE 2-37: Codes. 2010 Microchip Technology Inc. 44 37 88 34 32 32 76 29 20 27 64 24 08 22 52 19 96 16 40 14 84 11 8 92 2 67 6 41 0 16 Worst Case Codes (decimal) -3 db Bandwidth vs. Worst DS22250A-page 15 MCP4902/4912/4922 NOTES: DS22250A-page 16 2010 Microchip Technology Inc. MCP4902/4912/4922 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN FUNCTION TABLE Symbol VDD NC CS SCK SDI NC NC LDAC SHDN VOUTB VREFB VSS VREFA VOUTA Supply Voltage Input (2.7V to 5.5V) No Connection Chip Select Input Serial Clock Input Serial Data Input No Connection No Connection Synchronization Input. This pin is used to transfer DAC settings (Input Registers) to the output registers (VOUT) Hardware Shutdown Input DACB Output DACB Reference Voltage Input (VSS to VDD) Ground reference point for all circuitry on the device DACA Reference Voltage Input (VSS to VDD) DACA Output Function 3.1 Supply Voltage Pins (VDD, VSS) 3.5 Latch DAC Input (LDAC) VDD is the positive supply voltage input pin. The input supply voltage is relative to VSS and can range from 2.7V to 5.5V. The power supply at the VDD pin should be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 F (ceramic) to ground. An additional 10 F capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in application boards. VSS is the analog ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low-impedance connection. If an analog ground path is available in the application Printed Circuit Board (PCB), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. LDAC (latch DAC synchronization input) pin is used to transfer the input latch registers to their corresponding DAC registers (output latches, VOUT). When this pin is low, both VOUTA and VOUTB are updated at the same time with their input register contents. This pin can be tied to low (VSS) if the VOUT update is desired at the rising edge of the CS pin. This pin can be driven by an external control device such as an MCU I/O pin. 3.6 Hardware Shutdown Input (SHDN) SHDN is the hardware shutdown input pin. When this pin is low, both DAC channels are shut down. DAC output is not available during the shutdown. 3.7 Analog Outputs (VOUTA, VOUTB) 3.2 Chip Select (CS) VOUTA is the DAC A output pin, and VOUTB is the DAC B output pin. Each output has its own output amplifier. The DAC output amplifier of each channel can drive the output pin with a range of VSS to VDD. CS is the Chip Select input, which requires an active low signal to enable serial clock and data functions. 3.8 Voltage Reference Inputs (VREFA, VREFB) 3.3 Serial Clock Input (SCK) SCK is the SPI compatible serial clock input pin. 3.4 Serial Data Input (SDI) VREFA is the voltage reference input for DAC channel A, and VREFB is the reference input for DAC channel B. The reference on these pins is utilized to set the reference voltage on the string DAC. The input signal can range from VSS to VDD. These pins can be tied to VDD. SDI is the SPI compatible serial data input pin. 2010 Microchip Technology Inc. DS22250A-page 17 MCP4902/4912/4922 NOTES: DS22250A-page 18 2010 Microchip Technology Inc. MCP4902/4912/4922 4.0 GENERAL OVERVIEW TABLE 4-1: Device MCP4902 (n = 8) LSb OF EACH DEVICE Gain Selection LSb Size The MCP4902, MCP4912 and MCP4922 are dual voltage-output 8-bit, 10-bit and 12-bit DAC devices, respectively. These devices include input amplifiers, rail-to-rail output amplifiers, reference buffers for external voltage reference, shutdown and reset-management circuitry. The devices use an SPI serial communication interface and operate with a single supply voltage from 2.7V to 5.5V. The DAC input coding of these devices is straight binary. Equation 4-1 shows the DAC analog output voltage calculation. 1x VREF/256 2x (2* VREF)/256 MCP4912 1x VREF/1024 (n = 10) 2x (2* VREF)/1024 MCP4922 1x VREF/4096 (n = 12) 2x (2* VREF)/4096 where VREF is the external voltage reference. 4.1 EQUATION 4-1: ANALOG OUTPUT VOLTAGE (VOUT) VREF Dn 4.1.1 DC Accuracy INL ACCURACY Where: VREF Dn G = = = = = = = = = VOUT = ------------------------------ G n 2 n EXternal voltage reference DAC input code Gain Selection 2 for Integral Non-Linearity (INL) error is the maximum deviation between an actual code transition point and its corresponding ideal transition point, after offset and gain errors have been removed. The two end points (from 0x000 and 0xFFF) method is used for the calculation. Figure 4-1 shows the details. A positive INL error represents transition(s) later than ideal. A negative INL error represents transition(s) earlier than ideal. INL < 0 111 110 Actual Transfer Function The ideal output range of each device is: * MCP4902 (n = 8) (a) 0 V to 255/256 * VREF when gain setting = 1x. (b) 0 V to 255/256 * 2 * VREF when gain setting = 2x. * MCP4912 (n = 10) (a) 0 V to 1023/1024 * VREF when gain setting = 1x. (b) 0 V to 1023/1024 * 2 * VREF when gain setting = 2x. * MCP4922 (n = 12) (a) 0 V to 4095/4096 * VREF when Gain setting = 1x. (b) 0 V to 4095/4096 * 2 * VREF when gain setting = 2x. Note: See the output swing voltage specification in Section 1.0 "Electrical Characteristics". Digital Input Code 101 100 011 010 001 000 INL < 0 DAC Output Ideal Transfer Function FIGURE 4-1: 4.1.2 Example for INL Error. 1 LSb is the ideal voltage difference between two successive codes. Table 4-1 illustrates the LSb calculation of each device. DNL ACCURACY A Differential Non-Linearity (DNL) error is the measure of variations in code widths from the ideal code width. A DNL error of zero indicates that every code is exactly 1 LSb wide. 2010 Microchip Technology Inc. DS22250A-page 19 MCP4902/4912/4922 4.2.2 111 110 101 Digital Input Code 100 011 010 001 000 Narrow code, < 1 LSb DAC Output Actual transfer function Ideal transfer function VOLTAGE REFERENCE AMPLIFIERS Wide code, > 1 LSb The input buffer amplifiers for the MCP4902/4912/4922 devices provide low offset voltage and low noise. A Configuration bit for each DAC allows the VREF input to bypass the VREF input buffer amplifiers, achieving a Buffered or Unbuffered mode. Buffered mode provides a very high input impedance, with only minor limitations on the input range and frequency response. Unbuffered ( 4.2.3 POWER-ON RESET CIRCUIT FIGURE 4-2: 4.1.3 Example for DNL Accuracy. OFFSET ERROR An offset error is the deviation from zero voltage output when the digital input code is zero. The internal Power-on Reset (POR) circuit monitors the power supply voltage (VDD) during the device operation. The circuit also ensures that the DACs power-up with high output impedance ( 4.1.4 GAIN ERROR A gain error is the deviation from the ideal output, VREF- 1 LSb, excluding the effects of offset error. 4.2 4.2.1 Circuit Descriptions OUTPUT AMPLIFIERS Supply Voltages The DAC's outputs are buffered with a low-power, precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section 1.0 "Electrical Characteristics" for the analog output voltage range and load conditions. In addition to resistive load driving capability, the amplifier will also drive high capacitive loads without oscillation. The amplifier's strong outputs allow VOUT to be used as a programmable voltage reference in a system. Selecting a gain of 2 reduces the bandwidth of the amplifier in Multiplying mode. Refer to Section 1.0 "Electrical Characteristics" for the Multiplying mode bandwidth for given load conditions. 5V VPOR VDD - VPOR Transient Duration Time 10 Transient Duration (s) TA = 8 6 4 2 Transients Transients below above the the 4.2.1.1 Programmable Gain Block FIGURE 4-3: 0 1 The rail-to-rail output amplifier has configurable gain, allowing optimal full-scale outputs for different voltage reference inputs. The output amplifier gain has two selections, a gain of 1x ( 2 3 4 VDD - VPOR (V) 5 Typical Transient Response. DS22250A-page 20 2010 Microchip Technology Inc. MCP4902/4912/4922 4.2.4 SHUTDOWN MODE Op Amp VOUT The user can shut down each DAC channel selectively by using a software command or shut down all channels by using the SHDN pin. During Shutdown mode, most of the internal circuits in the channel that was shut down are turned off for power savings. The serial interface remains active, thus allowing a write command to bring the device out of the Shutdown mode. There will be no analog output at the channel that was shut down and the VOUT pin is internally switched to a known resistive load (500 k typical. Figure 4-4 shows the analog output stage during the Shutdown mode. The condition of the Power-on Reset circuit during the shutdown is as follows: a) b) Turned-off, if the shutdown occurred by the SHDN pin; On, if the shutdown occurred by the software. Power-Down Control Circuit Resistive Load 500 k Resistive String DAC FIGURE 4-4: Mode. Output Stage for Shutdown The device will remain in Shutdown mode until the SHDN pin is brought to high or a write command with 2010 Microchip Technology Inc. DS22250A-page 21 MCP4902/4912/4922 NOTES: DS22250A-page 22 2010 Microchip Technology Inc. MCP4902/4912/4922 5.0 5.1 SERIAL INTERFACE Overview 5.2 Write Command The MCP4902/4912/4922 devices are designed to interface directly with the Serial Peripheral Interface (SPI) port, which is available on many microcontrollers and supports Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SDI pin, with data being clocked-in on the rising edge of SCK. The communications are unidirectional, thus the data cannot be read out of the MCP4902/4912/4922. The CS pin must be held low for the duration of a write command. The write command consists of 16 bits and is used to configure the DAC's control and data latches. Register 5-1 to Register 5-3 detail the input register that is used to configure and load the DACA and DACB registers for each device. Figure 5-1 to Figure 5-3 show the write command for each device. Refer to Figure 1-1 and SPI Timing Specifications Table for detailed input and output timing specifications for both Mode 0,0 and Mode 1,1 operation. The write command is initiated by driving the CS pin low, followed by clocking the four Configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the selected DAC's input registers. The MCP4902/4912/4922 utilizes a double-buffered latch structure to allow both DACA's and DACB's outputs to be synchronized with the LDAC pin, if desired. Upon the LDAC pin achieving a low state, the values held in the DAC's input registers are transferred into the DAC's output registers. The outputs will transition to the value and held in the DACX register. All writes to the MCP4902/4912/4922 are 16-bit words. Any clocks past the 16th clock will be ignored. The Most Significant 4 bits are Configuration bits. The remaining 12 bits are data bits. No data can be transferred into the device with CS high. This transfer will only occur if 16 clocks have been transferred into the device. If the rising edge of CS occurs prior to that, shifting of data into the input registers will be aborted. 2010 Microchip Technology Inc. DS22250A-page 23 MCP4902/4912/4922 REGISTER 5-1: W-x A/B bit 15 W-x BUF W-x GA WRITE COMMAND REGISTER FOR MCP4922 (12-BIT DAC) W-0 SHDN W-x D11 W-x D10 W-x D9 W-x D8 W-x D7 W-x D6 W-x D5 W-x D4 W-x D3 W-x D2 W-x D1 W-x D0 bit 0 REGISTER 5-2: W-x A/B bit 15 W-x BUF W-x GA WRITE COMMAND REGISTER FOR MCP4912 (10-BIT DAC) W-0 SHDN W-x D9 W-x D8 W-x D7 W-x D6 W-x D5 W-x D4 W-x D3 W-x D2 W-x D1 W-x D0 W-x x W-x x bit 0 REGISTER 5-3: W-x A/B bit 15 Where: bit 15 W-x BUF W-x GA WRITE COMMAND REGISTER FOR MCP4902 (8-BIT DAC) W-0 SHDN W-x D7 W-x D6 W-x D5 W-x D4 W-x D3 W-x D2 W-x D1 W-x D0 W-x x W-x x W-x x W-x x bit 0 A/B: DACA or DACB Selection bit 1 = Write to DACB 0 = Write to DACA 1= 0= bit 14 BUF: VREF Input Buffer Control bit Buffered Unbuffered bit 13 GA: Output Gain Selection bit 1 = 1x (VOUT = VREF * D/4096) 0 = 2x (VOUT = 2 * VREF * D/4096) SHDN: Output Shutdown Control bit 1 = Active mode operation. VOUT is available. 0 = Shutdown the selected DAC channel. Analog output is not available at the channel that was shut down. VOUT pin is connected to 500 ktypical) D11:D0: DAC Input Data bits. Bit x is ignored. bit 12 bit 11-0 Legend R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown DS22250A-page 24 2010 Microchip Technology Inc. MCP4902/4912/4922 CS 0 SCK config bits SDI 12 data bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) (Mode 0,0) A/B BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC VOUT FIGURE 5-1: Write Command for MCP4922 (12-bit DAC). CS 0 SCK config bits SDI A/B BUF GA SHDN D9 12 data bits D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) (Mode 0,0) LDAC VOUT Note: X = "don't care" bits FIGURE 5-2: Write Command for MCP4912 (10-bit DAC). CS 0 SCK config bits SDI A/B BUF GA SHDN D7 12 data bits D6 D5 D4 D3 D2 D1 D0 X X X X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) (Mode 0,0) LDAC VOUT Note: X = "don't care" bits FIGURE 5-3: Write Command for MCP4902 (8-bit DAC). 2010 Microchip Technology Inc. DS22250A-page 25 MCP4902/4912/4922 NOTES: DS22250A-page 26 2010 Microchip Technology Inc. MCP4902/4912/4922 6.0 TYPICAL APPLICATIONS VDD C1 = 10 F C2 = 0.1 F VDD C1 C1 VREFA MCP49x2 VOUTA VREFB VOUTB VREFA MCP49x2 VOUTA VREFB VOUTB SDI AVSS SDO SCK LDAC CS0 AVSS VSS SDI C2 C1 VDD C2 The MCP4902/4912/4922 family of devices are general purpose DACs intended to be used in applications where a precision with low-power and moderate bandwidth is required. Applications generally suited for the devices are: * * * * * Set Point or Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery Powered) Motor Control Feedback Loop CS1 6.1 Digital Interface The MCP4902/4912/4922 utilizes a 3-wire synchronous serial protocol to transfer the DAC's setup and output values from the digital source. The serial protocol can be interfaced to SPI or Microwire peripherals that is common on many microcontroller units (MCUs), including Microchip's PIC(R) MCUs and dsPIC(R) DSCs. In addition to the three serial connections (CS, SCK and SDI), the LDAC signal synchronizes the two DAC outputs. By bringing down the LDAC pin to "low", all DAC input codes and settings in the two DAC input registers are latched into their DAC output registers at the same time. Therefore, both DACA and DACB outputs are updated at the same time. Figure 6-1 shows an example of the pin connections. Note that the LDAC pin can be tied low (VSS) to reduce the required connections from 4 to 3 I/O pins. In this case, the DAC output can be immediately updated when a valid 16-clock transmission has been received and CS pin has been raised. FIGURE 6-1: Diagram. Typical Connection 6.3 Layout Considerations 6.2 Power Supply Considerations The typical application will require a bypass capacitor in order to filter high-frequency noise. The noise can be induced onto the power supply's traces from various events such as digital switching or as a result of changes on the DAC's output. The bypass capacitor helps to minimize the effect of these noise sources. Figure 6-1 illustrates an appropriate bypass strategy. In this example, two bypass capacitors are used in parallel: (a) 0.1 F (ceramic) and (b) 10 F (tantalum). These capacitors should be placed as close to the device power pin (VDD) as possible (within 4 mm). The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. Inductively-coupled AC transients and digital switching noises can degrade the input and output signal integrity, and potentially reduce the device performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs and isolated outputs with proper decoupling, is critical for the best performance. Particularly harsh environments may require shielding of critical signals. Breadboards and wire-wrapped boards are not recommended if low noise is desired. 2010 Microchip Technology Inc. DS22250A-page 27 PIC(R) Microcontroller MCP4902/4912/4922 6.4 Single-Supply Operation 6.4.1.1 Decreasing Output Step Size The MCP4902/4912/4922 family of devices are rail-torail voltage output DAC devices designed to operate with a VDD range of 2.7V to 5.5V. Its output amplifier is robust enough to drive small-signal loads directly. Therefore, it does not require any external output buffer for most applications. If the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8V may be desired with about 200 V resolution per step. Two common methods to achieve a 0.8V range is to either reduce VREF to 0.82V or use a voltage divider on the DAC's output. Using a VREF is an option if the VREF is available with the desired output voltage range. However, occasionally, when using a low-voltage VREF, the noise floor causes SNR error that is intolerable. Using a voltage divider method is another option and provides some advantages when VREF needs to be very low or when the desired output voltage is not available. In this case, a larger value VREF is used while two resistors scale the output range down to the precise desired level. Example 6-1 illustrates this concept. Note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. 6.4.1 DC SET POINT OR CALIBRATION A common application for the DAC devices is digitally-controlled set points and/or calibration of variable parameters, such as sensor offset or slope. For example, the MCP4922 provides 4096 output steps. If the external voltage reference (VREF) is 4.096V, the LSb size is 1 mV. If a smaller output step size is desired, a lower external voltage reference is needed. EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION (a) Single Output DAC: MCP4901 MCP4911 MCP4921 VDD (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 VREF VDD R1 RSENSE VCC+ VO DAC VOUT VTRIP 0.1 uF Comparator R2 SPI 3-wire Dn V OUT = V REF G -----N 2 R2 Vtrip = V OUT -------------------- R1 + R2 VCC- G = Gain selection (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution DS22250A-page 28 2010 Microchip Technology Inc. MCP4902/4912/4922 6.4.1.2 Building a "Window" DAC When calibrating a set point or threshold of a sensor, typically only a small portion of the DAC output range is utilized. If the LSb size is adequate enough to meet the application's accuracy needs, the unused range is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF or VSS, then creating a "window" around the threshold has several advantages. One simple method to create this "window" is to use a voltage divider network with a pull-up and pull-down resistor. Example 6-2 and Example 6-4 illustrate this concept. EXAMPLE 6-2: SINGLE-SUPPLY "WINDOW" DAC MCP4901 MCP4911 MCP4921 (a) Single Output DAC: (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 VCC+ R3 R1 Rsense VCC+ VREF VDD Comparator Vtrip 0.1 F VCCVCCVOUT DAC SPI 3 R2 Dn V OUT = VREF G -----N 2 G = Gain selection (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution Thevenin Equivalent R 2 R3 R 23 = -----------------R2 + R 3 V 23 V CC+ R2 + VCC- R3 = ---------------------------------------------------R 2 + R3 VOUT R1 VO R23 V23 V OUT R23 + V 23 R1 V trip = ------------------------------------------R 2 + R23 2010 Microchip Technology Inc. DS22250A-page 29 MCP4902/4912/4922 6.5 Bipolar Operation Bipolar operation is achievable using the MCP4902/ 4912/4922 family of devices by using an external operational amplifier (op amp). This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. Example 6-3 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VREF instead of VSS, if a higher offset is desired. Also note that a pull-up to VREF could be used instead of R4, if a higher offset is desired. EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE VREF VREF VDD VOUT R3 R1 VIN+ 0.1 F MCP4901 MCP4911 MCP4921 2 (a) Single Output DAC: VCC+ VO VCC- (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 DAC SPI 3 Dn VOUT = V REF G -----N 2 VIN+ V OUT R4 = ------------------R3 + R 4 R4 R2 R2 VO = V IN+ 1 + ----- - VDD ----- R 1 R1 6.5.1 G = Gain selection (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution DESIGN EXAMPLE: DESIGN A BIPOLAR DAC USING EXAMPLE 6-3 WITH 12-BIT MCP4922 OR MCP4921 -R2 - 2.05 - 2.05 -------- = ------------ = -----------R1 V REF 4.1 R2 1 ----- = -R1 2 An output step magnitude of 1 mV with an output range of 2.05V is desired for a particular application. The following steps show the details: Step 1: Calculate the range: +2.05V - (-2.05V) = 4.1V. Step 2: Calculate the resolution needed: 4.1V/1 mV = 4100 Since 212 = 4096, 12-bit resolution is desired. Step 3:The amplifier gain (R2/R1), multiplied by VREF, must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1+R2), the VREF source needs to be determined first. If a VREF of 4.1V is used, solve for the gain by setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: If R1 = 20 k and R2 = 10 k, the gain will be 0.5. Step 4: Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. R4 2.05V + 0.5V REF 2 ---------------------- = ----------------------------------------- = -1.5VREF R3 + R 4 3 If R4 = 20 k, then R3 = 10 k DS22250A-page 30 2010 Microchip Technology Inc. MCP4902/4912/4922 6.6 Selectable Gain and Offset Bipolar Voltage Output Using a Dual DAC This circuit is typically used in Multiplier mode and is ideal for linearizing a sensor whose slope and offset varies. Refer to Section 6.9 "Using Multiplier Mode" for more information on Multiplier mode. The equation to design a bipolar "window" DAC would be utilized if R3, R4 and R5 are populated. In some applications, precision digital control of the output range is desirable. Example 6-4 illustrates how to use the MCP4902/4912/4922 to achieve this in a bipolar or single-supply application. EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET R2 VREFA VDD VOUTA R1 VCC+ R5 VCC+ Dual Output DAC: MCP4902 MCP4912 VREFB MCP4922 DACA VDD DACA (Gain Adjust) VOUTB R3 VO DACB SPI 3 DACB (Offset Adjust) R4 VCC- 0.1uF VCC- DA VOUTA = V REFA G A -----N 2 DB V OUTB = VREFB G B -----N 2 VOUTB R 4 + VCC- R3 V IN+ = ----------------------------------------------R3 + R4 R2 R2 V O = V IN+ 1 + ----- - V OUTA ----- R 1 R 1 Offset Adjust Gain Adjust GX = Gain selection (1x or 2x) N = DAC Bit Resolution DA, DB = Digital value of DAC (0-255) for MCP4902 = Digital value of DAC (0-1023) for MCP4912 = Digital value of DAC (0-4095) for MCP4922 Bipolar "Window" DAC using R4 and R5 Thevenin Equivalent V CC+ R4 + V CC- R 5 V45 = ------------------------------------------R4 + R5 VOUTB R 45 + V45 R 3 V IN+ = ---------------------------------------------R3 + R 45 R4 R5 R 45 = -----------------R4 + R5 R2 R2 V O = VIN+ 1 + ----- - V OUTA ----- R 1 R 1 Offset Adjust Gain Adjust 2010 Microchip Technology Inc. DS22250A-page 31 MCP4902/4912/4922 6.7 Designing a Double-Precision DAC Using a Dual DAC Step 1: Calculate the resolution needed: 4.1V/1 V = 4.1x106. Since 222 = 4.2x106, 22bit resolution is desired. Since DNL = 0.75 LSb, this design can be attempted with the MCP4922. Step 2: Since DACB's VOUTB has a resolution of 1 mV, its output only needs to be "pulled" 1/1000 to meet the 1 V target. Dividing VOUTA by 1000 would allow the application to compensate for DACB's DNL error. Step 3: If R2 is 100, then R1 needs to be 100 k. Step 4:The resulting transfer function is not perfectly linear, as shown in the equation of Example 6-5. Example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit DAC. This design is simply a voltage divider with a buffered output. As an example, if a application similar to the one developed in Section 6.5.1 "Design Example: Design a Bipolar DAC Using Example 6-3 with 12-bit MCP4922 or MCP4921" required a resolution of 1 V instead of 1 mV and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. EXAMPLE 6-5: SIMPLE, DOUBLE-PRECISION DAC WITH MCP4922 VREF VDD VOUTA DACA (Fine Adjust) R1 >> R2 VOUTB DACB (Course Adjust) 3 DA V OUTA = VREFA GA ------12 2 VOUTA R 2 + VOUTB R 1 V O = ----------------------------------------------------R 1 + R2 DB V OUTB = VREFB GB ------12 2 R2 0.1 F R1 VCC+ VO MCP4922 VDD MCP4922 SPI VCC- G = Gain selection (1x or 2x) D = Digital value of DAC (0- 4096) DS22250A-page 32 2010 Microchip Technology Inc. MCP4902/4912/4922 6.8 Building Programmable Current Source When working with very small sensor voltages, plan on eliminating the amplifier's offset error by storing the DAC's setting under known sensor conditions. Example 6-6 shows an example for building a programmable current source using a voltage follower. The current sensor (sensor resistor) is used to convert the DAC voltage output into a digitally-selectable current source. Adding the resistor network from Example 6-2 would be advantageous in this application. The smaller Rsense is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled with. The voltage divider, or "window", DAC configuration would allow the range to be reduced, thus increasing resolution around the range of interest. EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE VDD or VREF (a) Single Output DAC: MCP4901 MCP4911 MCP4921 VREF VDD VOUT VCC+ Load IL Ib DAC SPI 3-wire (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 VCC- RSENSE IL Ib = --- VOUT IL = -------------- ----------R sense + 1 where Common-Emitter Current Gain Dn VOUT = V REF G -----N 2 G = Gain select (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution 2010 Microchip Technology Inc. DS22250A-page 33 MCP4902/4912/4922 6.9 Using Multiplier Mode The MCP4902/4912/4922 family of devices use external reference, and these devices are ideally suited for use as a multiplier/divider in a signal chain. The common applications are: (a) Precision programmable gain/attenuator amplifiers and (b) Motor control feedback loop. The wide input range (0V - VDD) is in Unbuffered mode and near rail-to-rail range in Buffered mode: its bandwidth (> 400 kHz), selectable 1x/2x gain and low power consumption give maximum flexibility to meet the application's needs. To configure the MCP4902/4912/4922 family of devices for multiple applications, connect the input signal to VREF and serially configure the DAC's input buffer, gain and output value. The DAC's output can utilize any of Examples 6-1 to 6-6, depending on the application requirements. Example 6-7 is an illustration of how the DAC can operate in a motor control feedback loop. If the gain selection bit is configured for 1x mode ( EXAMPLE 6-7: MULTIPLIER MODE USING VREF INPUT VRPM_SET VRPM (a) Single Output DAC: MCP4901 MCP4911 MCP4921 VDD VREF SPI 3 ZFB VOUT VCC+ + (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 DAC - VCCRsense Dn V OUT = V REF G -----N 2 DS22250A-page 34 2010 Microchip Technology Inc. MCP4902/4912/4922 7.0 7.1 DEVELOPMENT SUPPORT Evaluation and Demonstration Boards The Mixed Signal PICtailTM Demo Board supports the MCP4902/4912/4922 family of devices. Please refer to www.microchip.com for further information on this products capabilities and availability. 2010 Microchip Technology Inc. DS22250A-page 35 MCP4902/4912/4922 NOTES: DS22250A-page 36 2010 Microchip Technology Inc. MCP4902/4912/4922 8.0 8.1 PACKAGING INFORMATION Package Marking Information 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP4922 E/P e3 1011256 14-Lead SOIC (150 mil) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP4922 E/SL e3 1011256 14-Lead TSSOP XXXXXX YYWW NNN Example: 4922E/ST 1011 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. 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MCP4902/4912/4922 /HDG 3ODVWLF 6PDOO 2XWOLQH 6/ 1DUURZ PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 b h 3 e h c A A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E 0,1 0,//,0(7(56 120 %6& %6& %6& %6& 5() 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2010 Microchip Technology Inc. DS22250A-page 39 MCP4902/4912/4922 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS22250A-page 40 2010 Microchip Technology Inc. MCP4902/4912/4922 /HDG 3ODVWLF 7KLQ 6KULQN 6PDOO 2XWOLQH 67 PP %RG\ >76623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 12 e b c A A2 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F L1 0,//,0(7(56 0,1 120 %6& %6& 5() 0$; L /HDG :LGWK E 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2010 Microchip Technology Inc. DS22250A-page 41 MCP4902/4912/4922 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22250A-page 42 2010 Microchip Technology Inc. MCP4902/4912/4922 APPENDIX A: REVISION HISTORY Revision A (April 2010) * Original Release of this Document. 2010 Microchip Technology Inc. DS22250A-page 43 MCP4902/4912/4922 NOTES: DS22250A-page 44 2010 Microchip Technology Inc. MCP4902/4912/4922 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) Device: MCP4902-E/P: MCP4902-E/SL: MCP4902T-E/SL: MCP4902: Dual 8-Bit Voltage Output DAC MCP4902T: Dual 8-Bit Voltage Output DAC (Tape and Reel) MCP4912: Dual 10-Bit Voltage Output DAC MCP4912T: Dual 10-Bit Voltage Output DAC (Tape and Reel) MCP4922: Dual 12-Bit Voltage Output DAC MCP4922T: Dual 12-Bit Voltage Output DAC (Tape and Reel) E = -40C to +125C (Extended) c) d) e) MCP4902-E/ST: MCP4902T-E/ST: f) Temperature Range: Package: MCP4912-E/P: MCP4912-E/SL: MCP4912T-E/SL: g) h) P SL ST = = = 14-Lead Plastic Dual In-Line (PDIP) 14-Lead Plastic Small Outline - Narrow (SOIC) 14-Lead Plastic Think Shrink Small Outline (TSSOP) i) j) MCP4912-E/ST: MCP4912T-E/ST: k) l) m) MCP4922-E/P: MCP4922-E/SL: MCP4922T-E/SL: n) o) MCP4922-E/ST: MCP4922T-E/ST: Extended temperature, PDIP package. Extended temperature, SOIC package. Extended temperature, SOIC package, Tape and Reel Extended temperature, TSSOP package. Extended temperature, TSSOP package, Tape and Reel Extended temperature, PDIP package. Extended temperature, SOIC package. Extended temperature, SOIC package, Tape and Reel Extended temperature, TSSOP package. Extended temperature, TSSOP package, Tape and Reel Extended temperature, PDIP package. Extended temperature, SOIC package. Extended temperature, SOIC package, Tape and Reel Extended temperature, TSSOP package. Extended temperature, TSSOP package, Tape and Reel 2010 Microchip Technology Inc. DS22250A-page 45 MCP4902/4912/4922 NOTES: DS22250A-page 46 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-129-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. DS22250A-page 47 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/05/10 DS22250A-page 48 2010 Microchip Technology Inc. |
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